The present invention relates to a clock supply circuit and control method thereof.
In a related art, there is known a configuration of supplying a clock signal only to a module which issues a request for a clock, and stopping to supply the clock signal to a module which does not need supply of a clock for power-saving formation of a system. There is also known a system of pertinently controlling power dissipation by making a frequency of a clock signal high or low in accordance with a load of a system processing or the like as a power management function.
Japanese Patent Application Publication No. 2003-58271 discloses a technology of switching a frequency of a clock in steps as necessary (hereinafter, referred to as clock gear) with an object of a reduction in power dissipation. Generally, the clock gear masks the clock signal based on a synchronizing signal for masking in correspondence with the earliest clock in a processor by using a gated clock buffer.